A multi-level converter can achieve high output voltage and large power output by improving its topological structure, and usually it includes at least one H-bridge circuit that consists of four power semiconductor switches. At present, the multi-level converter usually uses one of the following modulation modes to adjust its output voltage: sinusoidal pulse width modulation (SPWM), space vector pulse width modulation (SVPWM), selective harmonic elimination pulse width modulation (SHEPWM), staircase/square wave modulation, etc.
In the prior art, when the multi-level converter uses a modulation mode of SHEPWM or staircase/square wave modulation, driving two upper power semiconductor switches of the H-bridge circuit to be on-state simultaneously or driving two lower power semiconductor switches of the H-bridge circuit to be on-state simultaneously can enable the H bridge circuit to output a zero level, and thus enables the multi-level converter to output a zero level. When the multi-level converter uses a modulation mode of SHEPWM or staircase/square wave modulation, the switching frequency of the power semiconductor switches in each H-bridge circuit is relatively lower and a time span of outputting the zero level in the H-bridge circuit is longer. Therefore, during a period of the zero level outputted by the H-bridge circuit, if the power semiconductor switches in the H-bridge circuit cannot be reasonably driven to be on, the losses of the power semiconductor switches in the H-bridge circuit will be seriously uneven, which reduces the useful lifetime of the H-bridge circuit.
Therefore, it is an urgent problem to be solved how to reasonably drive the power semiconductor switches in the H-bridge circuit to be on during zero levels outputted by the H-bridge circuit in the multi-level converter.